Processor bus arrangement

ABSTRACT

A processor bus arrangement including several data processing units, each connected to a line system specified as a bus. The bus includes connection units and bus segments, where the bus segments are connected to the bus in a seperable manner through the connection units. This guarantees that the functional units, arranged on the bus, carry out the information thereof, by means of the bus and may carry out an exchange independently of other functional units. Furthermore, other functional units in different groups may carry out an information exchange simultaneously, by means of the bus. As the connection units perform the function of the defined combinatory connection of the signal lines, the bus segments generate the physical connections between the connection units. This ensures that the connection units carry out the information exchange with as many connected functional units as required. The information path from a functional unit can be switched by toggling to selected functional units by simultaneous connection to several functional units or by bridging non-participating functional units. One method of switching the circuitry of the connection unit is by using a multiplexer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a National Phase of International ApplicationPCT/DE01/03651, filed Sep. 21, 2001.

FIELD OF THE INVENTION

The present invention relates to a processor bus arrangement having afirst and a second data processing unit, each of which is connected to asystem of lines combined as a bus.

BACKGROUND OF THE INVENTION

The most common connecting structures between the functional units ofcircuits, in particular computers, are buses. Such a bus can beimplemented either internal to a chip or between chips, for example asthe system bus of a computer that exchanges data between the individualfunctional units. In the simplest case, the bus forms a node betweenline segments that realize the connections to the functional units withtaps arranged in a star configuration. However, the bus arrangements offunctional units described in summary by Kain in “Advanced ComputerArchitecture” (ISBN 0-13-007741-0), pp. 376-385 with the followingtopologies are also common: 1. individual point-to-point connection, 2.bus with bus controller, 3. multiple buses, 4. crosspoint switchingsystem, 5. n-dimensional assigned functional units, 6. tree structures,7. ring structures, 8. multilayer network with intermediate connections,9. hierarchical structures.

To prevent information collisions from occurring on the bus, only onefunctional unit at a time may transmit its information onto the bus. Tocontrol such information exchange, the functional units are providedwith interfaces which for the most part are mechanically andelectrically specified, and are standardized, and thus ensure the timesequencing of allowed bus signals for the individual components.

The greatest disadvantage of prior art bus systems can be seen here inthat only a single data transport can take place at any point in time.This leads to bottlenecks in data transmission on the bus, while theprocessing speed of the individual functional units is not fullyutilized. Moreover, there are clear physical limits on improvingutilization of the processing speed of the system by increasing the datatransmission rate on the bus through increases in the computer clockspeed.

Even the known prior art method of prefetching is only effective to alimited extent in achieving the desired utilization of the processingspeed of the CPU, since the commands that are loaded in advance in thismethod must of necessity be discarded if the program conditions requireit in the course of executing the program. As a result, the speedincrease achieved is in part rendered ineffective in the processing ofcommands by the CPU.

Yet another method known from prior art, that of temporarily storingfrequently needed recent commands, and also data, in a cache memory andthus avoiding additional data transmission across the bus, brings only alimited gain in increasing the processing speed of the CPU.

It is also necessary to mention a vector processor solution described in“Computer Architecture” by Michael J. Flynn (ISBN 0-86720-204-39), pp.434-438. Here, data sets to be processed with the same operation, butwhich are prepared by different functional units, are combined inso-called vector registers. Within such a vector structure of specificlength, these data sets are supplied as indexed blocks for processingwith the required operation, e.g. ADD, MULTIPLY.

Thus, the greatest disadvantage in increasing the data transmission rateon a bus in prior art clearly consists in that it is not possible forfunctional units acting independently of one another to use the bus inparallel.

The object of the present invention is making it possible for functionalunits connected to a bus to communicate simultaneously and independentlyof one another.

SUMMARY OF THE INVENTION

The solution in accordance with the present invention includes a busthat has a connection unit and bus segments, wherein the bus segmentsare connected to the bus in a separable manner by means of theconnection unit.

The present invention ensures that the functional units that arearranged on the bus and exchange their information through the bus canperform this exchange independently of other functional units. Moreover,other functional units in additional groups can also carry out aseparate information exchange through this bus at the same time. Whilethe connection units perform the function of defined combinatorialconnection of the signal lines, the bus segments provide lineconnections between the connection units.

An advantageous embodiment of the solution in accordance with theinvention consists in that multiple paths, which unidirectionally orbidirectionally perform data transmission in the connection unit, arearranged in the connection unit.

This method ensures that the connection unit carries out informationexchange with any desired number of functional units arranged thereon.The information paths from a functional unit can be assigned to selectedfunctional units by switchover or to multiple functional units at thesame time by add-on switching. Depending on equipment, the multiplepaths can be unidirectional or bidirectional. In the unidirectionalimplementation of the connection unit, care is taken that in the choiceof communicating functional units, only one functional unit can transmitat a time, while all other functional units participating in thecommunication can only receive information.

In the bidirectional implementation of the connection unit, theconnected functional units can send and receive. The connection unituses an additional directional channel (right, left) to ensure theassociated directional dependence of the information exchange.

Another advantageous embodiment of the solution in accordance with theinvention consists in that a second and a third connection unit arearranged in a chain with the first connection unit as a repeaterstructure.

This implementation makes special provision that an information exchangeon the bus takes place not only with functional units that areimmediately adjacent to the connection unit, but also that, in such anadvantageous arrangement of the connection units, their implementationas a repeater structure can be optimized in technical and economicterms. It also simplifies the bus structure as a whole when theconnection unit is designed to be chainable as a repeater structure. Tothis extent, the connection units can be conceptualized as components ofa matrix with favorably arranged interfaces, and it also simplifies thedesign of the bus segments to likewise be a number of repeatablyarranged basic forms.

A special advantageous embodiment of the solution in accordance with theinvention provides that the connection units of the repeater structureare arranged chained together in a star and/or ring shape. Particularattention is paid here in the design of the processor arrangement inaccordance with the invention to achievable signal propagation times inthe exchange of information between functional units that are favorablyarranged relative to one another and which frequently communicate withone another. Optimal adaptation in this regard can be obtained by thechoice of the processor bus arrangement, whether as a ring, a chain ormixed forms.

Another particular advantageous embodiment of the invention providesthat the connection units are wired to bridge across adjacent connectionunits. In order to keep signal propagation times low, when connectionunits are traversed for which the connected functional units are notparticipating in the information exchange, they are bridged, i.e. thenumber of gates traversed and the signal path lengths per connectionunit are minimized here.

Another particular advantageous embodiment of the invention providesthat termination units are arranged at each end of the chained repeaterstructure of connection units.

In this context, connection units equipped as termination units are usedthat can be connected at their connection sides only to the singledirectly adjacent connection unit. No additional connections forconnecting to other connection units are provided. The termination unitprovides a default state for the control of the connection units of thebus, which is assumed when no signals from the controlling processingunit are present.

An advantageous embodiment of the solution in accordance with theinvention provides that the termination unit is switched onto therepeater structure as a terminator without additional connection, orthat it is also directly connected to connection units by a tap,shortening signal propagation times. A special form of a terminationunit is implemented in this context, wherein an additional connection toa desired connection unit is made through the necessary bus segments onthe connection side, in addition to the directly adjacent connectionunit. This connection option is used to reduce signal propagation timesfor functional units that communicate under conditions where signalpropagation time is critical.

An important advantageous implementation of the solution in accordancewith the invention provides that the connection unit is constructed ofmultiplexers. Implementation of the connection unit with multiplexercomponents is used by preference. In this way, the switching functionscan be realized with minimum component count.

Another important advantageous implementation of the solution inaccordance with the invention provides that the multiplexer gatefunction is expanded so as to be switchable to the logical operations ORand XOR. For additional tasks on the bus, a functional switchover isprovided that performs signal combinations with other logical operationssuch as OR or XOR.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood with reference to theattached drawings described below:

FIG. 1 shows a block diagram of the processor bus arrangement with theassignment of the functional units to the connection units and bussegments;

FIG. 2 shows a functional diagram of the multiplexer embodiment of aconnection unit which implements combination of the bidirectional ICUright/left data path with a crossing track of a likewise bidirectionaldata path to connect two functional units;

FIG. 3 shows a functional diagram of the multiplexer embodiment of aconnection unit which implements combination of the bidirectional ICUright/left data path with two crossing tracks of likewise bidirectionaldata paths to connect two functional units; and

FIG. 4 is a functional diagram of OR function expansion of a multiplexerconnection unit.

DETAILED DESCRIPTION

As can be seen in FIG. 1, the bus 1 consists of bidirectional connectionunits 2 and bus segments 3. The connection units are of a two-trackdesign and carry the data paths ICUBUS0R 79 and ICUBUS0L 78 in the firsttrack, and the data paths ICUBUS1R 77 and ICUBUS1L 76 in the secondtrack. Arranged on this bus 1 are the IOU functional unit 10, AGUfunctional unit 9, PCU functional unit 8, GPU functional unit 7, RFUfunctional unit 6, which in turn consists of multiple DPU functionalunits 5.

The ends of the bus are equipped with termination units 4, which uponloss of external bus control signals internally implement the bus with adefault state labeled “0”. The data paths ICUBUS1L 76 and ICUBUS0L 78are branched off via bus segments 3 and fed by means of the terminationunits 4 to the connection units 2 arranged at the end of bus 1, reducingpropagation time.

FIG. 2 shows how the multiplexer implementation of the illustratedconnection unit combines the bidirectional ICU right/left data path witha crossing track of a likewise bidirectional data path to connect twofunctional units, here by way of example the RFU functional unit 6 and aMEM functional unit not shown in FIG. 1. Here, the ICU right data pathis routed through the ICU_In_Right signal line 21, and with appropriate“pass-through” control is routed directly through the first output gate19 to the ICU_Out_Right signal line 23. The ICU left data path leadsthrough the ICU_In_Left signal line 24, and with appropriate“pass-through” control is routed directly through the fourth output gate14 to the ICU_Out_Left signal line 22.

Moreover, the ICU right data path is routed through the input signalamplifier 11, and with appropriate control in “switchover” is routedeither through the second output gate 12 to the MEM_Out_Slc1_Rightsignal line 26 or through the third output gate 13 to theRFU_Out_Slc1_Right signal line 27. In contrast, the ICU left data pathis routed through the input signal amplifier 20, and with appropriatecontrol in “switchover” is routed either through the fifth output gate17 to the MEM_Out_Slc1_Left signal line 30 or through the sixth outputgate 18 to the RFU_Out_Slc1_Right signal line 32.

The MEM right data path passes through the MEM_In_Slc1_Right signal line25, either directly through the third output gate 13 to theRFU_Out_Slc1_Right signal line 27 with appropriate “pass-through”control, or through the first logic gate 15 and the first output gate 19to the ICU_Out_Right signal line 23 with appropriate “switchover”control.

In addition, it is important to note that the MEM right data path inSlice0 passes through the MEM_In_Slc0_Right signal line 34 directly tothe RFU_Out_Slc0_Right signal line 35.

The MEM left data path passes through the MEM_In_Slc1_Left signal line29, either directly through the sixth output gate 18 to theRFU_Out_Slc1_Left signal line 32 with appropriate “pass-through”control, or through the second logic gate 16 and the second output gate14 to the ICU_Out_Left signal line 22 with appropriate “switchover”control.

In addition, it is important to note that the MEM left data path inSlice0 passes through the MEM_In_Slc0_Left signal line 38 directly tothe RFU_Out_Slc0_Left signal line 40. The RFU right data path in Slice1passes through the RFU_In_Slc1_Right signal line 28, either directlythrough the second output gate 12 to the MEM_Out_Slc1_Right signal line26 with appropriate “pass-through” control, or through the first logicgate 15 and the first output gate 19 to the ICU_Out_Right signal line 23with appropriate “switchover” control. In addition, it is important tonote that the RFU right data path in Slice0 passes through theRFU_In_Slc0_Right signal line 36 directly to the MEM_Out_Slc0_Rightsignal line 33.

The RFU left data path in Slice1 passes through the RFU_In_Slc1_Leftsignal line 31, either directly through the fifth output gate 17 to theMEM_Out_Slc1_Left signal line 30 with appropriate “pass-through”control, or through the second logic gate 16 and the second output gate14 to the ICU_Out_Left signal line 22 with appropriate “switchover”control.

In addition, it is important to note that the RFU left data path inSlice0 passes through the RFU_In_Slc0_Left signal line 39 directly tothe MEM_Out_Slc0_Left signal line 37.

FIG. 3 shows how the multiplexer implementation of the illustratedconnection unit combines the bidirectional ICU right/left data path withtwo crossing tracks of likewise bidirectional data paths to connect twofunctional units, here by way of example the RFU functional unit 6 and aMEM functional unit not shown in FIG. 1. Here, the ICU right data pathis routed through the ICU_In_Right signal line 21, and with appropriate“pass-through” control is routed directly through the seventh outputgate 49 to the ICU_Out_Right signal line 23. The ICU left data pathleads through the ICU_In_Left signal line 24, and with appropriate“pass-through” control is routed directly through the tenth output gate44 to the ICU_Out_Left signal line 22.

Moreover, the ICU right data path for Slice1 is amplified by the thirdinput signal amplifier 41, and with appropriate control in “switchover”is routed either through the eighth output gate 42 to theMEM_Out_Slc1_Right signal line 26 or through the ninth output gate 43 tothe RFU_Out_Slc1_Right signal line 27. Similarly, the ICU right datapath for Slice0 is amplified by the third input signal amplifier 41, andwith appropriate control in “switchover” is routed through the thirdlogic gate 45 and either through the fifteenth output gate 56 to theMEM_Out_Slc0_Right signal line 33 or through the sixteenth output gate57 to the RFU_Out_Slc0_Right signal line 35.

In contrast, the ICU left data path for Slice1 is amplified by thefourth input signal amplifier 58, and with appropriate control in“switchover” is routed either through the ninth logic gate 59 and theeleventh output gate 47 to the MEM_Out_Slc1_Left signal line 30 orthrough the ninth logic gate 59 and the twelfth output gate 48 to theRFU_Out_Slc1_Right signal line 32.

The ICU left data path for Slice0 is likewise amplified by the fourthinput signal amplifier 58, but with appropriate control in “switchover”is routed either through the fourteenth output gate 50 to theMEM_Out_Slc0_Left signal line 37 or through the thirteenth output gate55 to the RFU_Out_Slc0_Left signal line 40.

The MEM right data path for Slice1 passes through the MEM_In_Slc1_Rightsignal line 25, either directly through the ninth output gate 43 to theRFU_Out_Slc1_Right signal line 27 with appropriate “pass-through”control, or through the fourth logic gate 5 1 and the fifth logic gate53 and the seventh output gate 49 to the ICU_Out_Right signal line 23with appropriate “switchover” control.

Likewise, the MEM right data path for Slice1 passes through theMEM_In_Slc1_Right signal line 25, but then through the third logic gate45, either through the fifteenth output gate 56 to theMEM_Out_Slc0_Right signal line 33, or through the sixteenth output gate57 to the RFU_Out_Slc0_Right signal line 35, in accordance with the“switchover” control.

The MEM right data path for Slice0 passes through the MEM_In_Slc0_Rightsignal line 34, either directly through the sixteenth output gate 57 tothe RFU_Out_Slc0_Right signal line 35 with appropriate “pass-through”control, or through the tenth logic gate 60, the fifth logic gate 53 andthe seventh output gate 49 to the ICU_Out_Right signal line 23 withappropriate “switchover” control.

The MEM left data path for Slice1 passes through the MEM_In_Slc1_Leftsignal line 29, then either directly through the twelfth output gate 48to the RFU_Out_Slc0_Left signal line 32 with appropriate “pass-through”control, or through the sixth logic gate 46 and the seventh logic gate52 as well as the tenth output gate 44 to the ICU_Out_Left signal line22 with appropriate “switchover” control.

In addition, the MEM left data path in Slice0 passes through theMEM_In_Slc0_Left signal line 38, either directly through the thirteenthoutput gate 55 to the RFU_Out_Slc0_Left signal line 40 with appropriate“pass-through” control, or through the eighth logic gate 54 and theseventh logic gate 52 as well as the tenth output gate 44 to theICU_Out_Left signal line with appropriate “switchover” control.Moreover, the MEM left data path in Slice0 passes through theMEM_In_Slc0_Left signal line 38 through the ninth logic gate 59 withappropriate “switchover” control, and either through the eleventh outputgate 47 to the MEM_Out_Slc1_Left signal line 30 or through the twelfthoutput gate 48 to the RFU_Out_Slc1_Left signal line 32.

The RFU right data path in Slice1 passes through the RFU_In_Slc1_Rightsignal line 28, either directly through the eighth output gate 12 to theMEM_Out_Slc1_Right signal line 26 with appropriate “pass-through”control, or through the fourth logic gate 51 and the fifth logic gate 53and the seventh output gate 49 to the ICU_Out_Right signal line 23 withappropriate “switchover” control.

The RFU right data path in Slice1 also passes from the RFU_In_Slc1_Rightsignal line 28 through the third logic gate and either through thefifteenth output gate 56 to the MEM_Out_Slc0_Right signal line 33 orthrough the sixteenth output gate 57 to the RFU_Out_Slc0_Right signalline 35 with appropriate “switchover” control.

Moreover, the RFU right data path in Slice0 passes from theRFU_In_Slc0_Right signal line 36, either directly through the fifteenthoutput gate 56 to the MEM_Out_Slc0_Right signal line 33 with appropriate“pass-through” control, or through the tenth logic gate 60 and the fifthlogic gate 53 and the seventh output gate 49 to the ICU_Out_Right signalline 23 with appropriate “switchover” control.

The RFU left data path in Slice1 passes from the RFU_In_Slc1_Left signalline 31, either directly through the eleventh output gate 47 to theMEM_Out_Slc1_Left signal line 30 with appropriate “pass-through”control, or through the sixth logic gate 46 and the seventh logic gate52 and the tenth output gate 44 to the ICU_Out_Left signal line 22 withappropriate “switchover” control.

The RFU left data path in Slice0 passes from the RFU_in_Slc0_Left signalline 39, either directly through the fourteenth output gate 50 to theMEM_Out_Slc0_Left signal line 37 with appropriate “pass-through”control, or through the eighth logic gate 54 and the seventh logic gate52 and the tenth output gate 44 to the ICU_Out_Left signal line 22 withappropriate “switchover” control. Moreover, the RFU left data path inSlice0 passes from the RFU_in_Slc0_Left signal line 39 through the ninthlogic gate 59 with appropriate “switchover” control and either throughthe eleventh output gate 47 to the MEM_Out_Slc1_Left signal line 30 orthrough the twelfth output gate 48 to the RFU_Out_Slc1_Left signal line32.

In the functional diagram of OR function expansion of a multiplexerconnection unit shown in FIG. 4, an ICU right data path passes from theICU_right_in signal line 65 to an icuwmux subunit 70 and to an icurmuxor/multiplex subunit 69 whose output is connected to the ICU_right_outsignal line 67. An ICU left data path passes from the ICU_left_in signalline 66 to an icuwmux subunit 70 and to an iculmux or/multiplex subunit68 whose output is connected to the ICU_left_out signal line 64. TheRFU-in signal line 75 is connected to the corresponding second inputs oficurmux or/multiplex subunit 69 and iculmux or/multiplex subunit 68 forthe required signal processing. In addition, on the curmux or/multiplexsubunit 69 and iculmux or/multiplex subunit 68 is an ICUORMUX_ctrlsignal line 71 whose logical assignment can be used for functionalselection of the multiplex function or OR function expansion for the twosubunits. Gate control for the subunits is performed using theICULMUX_ctrl signal line 72 connected to the iculmux or/multiplexsubunit 68 and the ICURMUX_ctrl signal line 73 connected to the icurmuxor/multiplex subunit 69.

While there have been described what are believed to be the preferredembodiments of the present invention, those skilled in the art willrecognize that other and further changes and modifications may be madethereto without departing from the spirit of the invention, and it isintended to claim all such changes and modifications as all within thetrue scope of the invention

1-11. (canceled)
 12. A processor bus arrangement comprising achip-internal parallel processor system having a first and a second dataprocessing unit, each of which is connected to a system of linescombined as a bus wherein; the bus has a connection unit and bussegments; the bus segments are connected to the bus in a separablemanner by means of the connection unit; multiple paths, whichunidirectionally or bidirectionally perform data transmission, arearranged in the connection unit; and a second and a third connectionunit are arranged in a chain with a first connection unit as a repeaterstructure, wherein the connection units of the repeater structure arearranged chained together in one of a star and a ring, and wherein theconnection units are arranged to bridge across adjacent connectionunits.
 13. The processor bus arrangement according to claim 12, whereina termination unit is arranged at each end of the chained repeaterstructure of said connection units.
 14. The processor bus arrangementaccording to claim 13, wherein a termination unit is switched onto therepeater structure as a terminator without additional connection. 15.The processor bus arrangement according to claim 13, wherein atermination unit is directly connected to connection units.
 16. Theprocessor bus arrangement according to claim 12, wherein the connectionunit comprises a multiplexer.
 17. The processor bus arrangementaccording to claim 16, wherein the multiplexer gate function is expandedto the logical operations OR and XOR.
 18. The processor bus arrangementaccording to claim 16, wherein the multiplexer is a bidirectionalmultiplexer wherein; an ICU_IN_RIGHT signal line is connected to a firstinput of a first input signal amplifier and simultaneously to a firstinput of a first output gate, whose output-is connected to theICU_Out_Right signal line; the output of the first input signalamplifier is connected to a first input of a second output gate andsimultaneously to a first input of a third output gate, the second inputis connected to the MEM_In_SL1_Right signal line and simultaneously to afirst input of a first logic gate and wherein the output is connectedthe second input of the first output gate; the output of the secondoutput gate is connected to a signal line MEM_Out_SLC1_Right and itsinput is connected to a signal line RFU_In_Slc1_Right and simultaneouslyto the second of the first logic gate, the output of the third outputgate is connected to an RFU_Out_Slc1_Right signal line, wherein anICU_IN_Left signal line is connected to an input of a second inputsignal amplifier and simultaneously to a first input of a fourth outputgate and its output is connected to an ICU_Out_Left signal line; theoutput of the second input signal amplifier is connected to a firstinput of a fifth output gate and simultaneously to a first input ofsixth output gate whose second input is connected to the MEM_In_SL1_Leftsignal line and simultaneously to a first input of a second logic gateand whose output is connected to the second input of the fourth outputgate; the output of the fifth output gate is connected to a signal lineMEM_Out_SLC1_Left and the second input of a fifth output gate isconnected to a signal line RFU_In_Slc1_Left and simultaneously to thesecond input of the second logic gate; the output of the sixth outputgate is connected to an RFU_Out_Slc1_Left signal line; a signal lineRFU_In_Slc0_Right is connected to a signal line MEM_Out_Slc0_Right; asignal line RFU_Out_Slc0_Right is connected to a signal lineMEM_In_Slc0_Right; a signal line RFU_In_Slc0_Left is connected to asignal line MEM_Out_Slc0_Left; and a signal line RFU_Out_Slc0_Left isconnected to a signal line MEM_Out_Slc0_Left.
 19. The processor busarrangement according to claim 16, wherein the multiplexer is a dualslice bidirectional multiplexer wherein; an ICU_IN_RIGHT signal line isconnected to a first input of a third input signal amplifier andsimultaneously to a first input of a seventh output gate and whoseoutput is connected to the ICU_Out_Right signal line; the output of thethird input signal amplifier is connected to a first input of an eighthoutput gate and simultaneously to a first input of a ninth output gateas well as to a first input of a third logic gate; the second input ofthe ninth output gate is connected to the MEM_In_SL1_Right signal lineand simultaneously to the second input of the third logic gate as wellas a first input of a fourth logic gate and whose output is connected toa first input of a fifth logic gate; the output of the eighth outputgate is connected to a signal line MEM_Out_SLC1_Right and its secondinput is connected in turn to a signal line RFU_In_Slc1_Right andsimultaneously to the third input of the third logic gate and the secondinput of the fourth logic gate; the output of the ninth output gate isconnected to an RFU_Out_Slc1_Right signal line; the output of the thirdlogic gate is connected to a first input of a fifteenth output gate andsimultaneously to a first input of a sixteenth output gate whose outputis in turn connected to the RFU_Out_Slc0_Right signal line; theRFU_In_Slc0_Right signal line is connected to the second input of thefifteenth output gate and also to a first input of a tenth logic gatewherein its output is connected to the second input of the fifth logicgate; the second input of the tenth logic gate is connected to theMEM_In_Slc0_Right signal line and also to the second input of thesixteenth output gate; the output of the fifteenth output gate isconnected to the MEM_Out_Slc0_Right signal line; the output of the fifthlogic gate is connected to the second input of the seventh output gate;an ICU_IN_Left signal line is connected to a first input of a fourthinput signal amplifier and simultaneously to a first input of a tenthoutput gate and its output is connected to the ICU_Out_Left signal line;the output of the fourth input signal amplifier is connected to a firstinput of a thirteenth output gate and simultaneously to a first input ofa fourteenth output gate as well as to a first input of a ninth logicgate; the second input of the fourteenth output gate is connected to theRFU_In_SLc0_Left signal line and simultaneously to the second input ofthe ninth logic gate as well as to a first input of an eighth logic gateand whose output is connected to a first input of a seventh logic gate;the output of the thirteenth output gate is connected to a signal lineRFU_Out_SLC0_Left and its second input in turn is connected to a signalline MEM_In_Slc0_Left and simultaneously to the third input of the ninthlogic gate and also to the second input of the eighth logic gate; theoutput of the fourteenth output gate is connected to a MEM_Out_Slc0_Leftsignal line; the output of the ninth logic gate is connected to a firstinput of an eleventh output gate and simultaneously to a first input ofa twelfth output gate whose output in turn is connected to theRFU_Out_Slc1_Left signal line; the MEM_In_Slc1_Left signal line isconnected to the second input of the twelfth output gate and also to afirst input of a sixth logic gate wherein its output is connected to thesecond input of the seventh logic gate; the second input of the sixthlogic gate is connected to the RFU_In_Slc1_Left signal line and also tothe second input of the eleventh output gate whose output is connectedto the MEM_Out_Slc1_Left signal line; and the output of the seventhlogic gate is connected to the second input of the seventh output gate.